1. Field of the Invention
The present invention relates generally to an automatic gain control circuit and, more particularly, is directed to a gain controlled amplifying circuit whose gain is controlled by the automatic gain control circuit.
2. Description of the Prior Art
Prior to "BRIEF DESCRIPTION OF THE DRAWINGS", let us first explain an example of the prior art with reference to the drawings in order to understand the problems inherent in the prior art more clearly.
A prior-art magnetic disk apparatus utilizes an automatic gain control circuit to correct a reproduced signal from a magnetic head so that it may fall within a predetermined signal level range. FIG. 1 is a block diagram showing a prior-art feedback-type automatic gain control circuit which is generally designated by reference numeral 1.
As shown in FIG. 1, a reproduced signal S.sub.RF from, for example, a magnetic disk (not shown) or the like is supplied to a voltage controlled amplifying circuit 2. The voltage controlled amplifying circuit 2 will be described in detail with reference to FIG. 2.
Referring to FIG. 2, it will be seen that the voltage controlled amplifying circuit 2 is comprised of transistors Q1, Q2 connected in a differential amplifying circuit configuration and transistors Q3, Q4 and Q5, Q6, each transistor pair being connected in a differential amplifying circuit configuration. The output currents of the transistors Q1 and Q2 are respectively supplied to the emitters of the transistors Q3, Q4 and to the emitters of the transistors Q5, Q6, thus resulting in a multiplying circuit arrangement being formed.
The emitters of the transistors Q1 and Q2 are connected by a resistor 3, and are respectively connected to constant current sources 4 and 5 and an input signal is supplied to their bases.
A control voltage Vc is supplied to the bases of the transistors Q3, Q4 and of the transistors Q5, Q6, and load resistors 7 and 8 are commonly connected to the collectors of the transistors Q3, Q5 and to the collectors of the transistors Q4, Q6, respectively.
Thus, when a signal source 9 having a voltage V.sub.RF is connected between the bases of the transistors Q1 and Q2, as shown in FIG. 3, the voltage controlled amplifying circuit 2 generates as a terminal voltage across the load resistors 7 and 8 an output signal which is amplified by a gain G given by the following equation ##EQU1## where R.sub.E is the resistance value of the resistor 3 and R.sub.L is the resistance value of the load resistors 7 and 8.
In this case, V.sub.T represents the thermal voltage of each of the transistors Q1, Q2, Q3, Q4, Q5 and Q6 and is expressed by the following equation ##EQU2## where k is the Boltzman's constant, T is the absolute temperature and q is the charge of an electron.
Thus, when the reproduced signal S.sub.RF instead of the signal from the signal source 9 is supplied to the transistors Q1 and Q2 and the control voltage Vc is controlled in response to the level of the reproduced signal S.sub.RF, the voltage controlled amplifying circuit 2 can generate the output signal having a predetermined level.
To be more concrete, referring back to FIG. 1, an output signal S.sub.0 of the voltage controlled amplifying circuit 2 is supplied to a peak detecting circuit 10, and a detected signal S.sub.P from the peak detecting circuit 10 is supplied to a gain control circuit 11.
The gain control circuit 11 generates a control signal S.sub.C whose level changes with the level of the detected signal S.sub.p. This control signal S.sub.C is supplied to the voltage controlled amplifying circuit 2 as a control voltage Vc.
Even when the signal level of the reproduced signal S.sub.RF fluctuates or pulses, it is possible to obtain an output signal S.sub.0 whose signal level is at a predetermined level.
The reproduced signal S.sub.RF from the magnetic head is so selected that its signal level rises up from zero at every predetermined period as shown in FIG. 4A.
During a time period T1 in which the reproduced signal S.sub.RF goes to a high level, the control signal S.sub.C changes in an region ARD (hereinafter, referred to as an operation region) in which the gain G of the voltage controlled amplifying circuit 2 changes substantially linearly relative to the control voltage Vc so that the output signal S.sub.0 is controlled to have a predetermined signal level, as shown in FIG. 3. During a time period T2 in which the signal level of the reproduced signal S.sub.RF is zero, the control signal S.sub.C is displaced beyond the operation region ARD up to a region ARF (hereinafter, referred to as a saturation region) in which the gain G is not changed even when the control voltage V.sub.C is changed.
There is then presented such a problem that immediately after the reproduced signal S.sub.RF goes to a high level from zero, an over-shoot occurs in the envelope of the output signal S.sub.0 as shown in FIG. 4B during the period in which the signal level of the control signal S.sub.C goes to a predetermined level in the operation region ARD from the saturation region ARF.
To solve the above-mentioned problem, the following proposals are made, which are disclosed in Japanese Patent Publications Nos. 61-61570 and 61-61726. According to these proposals, during the time period T2 in which the signal level of the reproduced signal S.sub.RF is zero level, the gain G is maintained to a predetermined value by controlling the control signal S.sub.C to have a predetermined level, whereby a period (hereinafter, referred to as an attack time) in which the signal level of the reproduced signal S.sub.RF rises from zero level and the signal level of the output signal S.sub.0 falls to a predetermined level is reduced.
As described above, the control signal S.sub.c is maintained to have the predetermined level and the displacement of the control signal S.sub.C is sufficiently reduced around a time at which the signal level of the reproduced signal rises. Thus, it is possible to obtain an automatic gain control circuit which can reduce the duration of the attack time.
In the voltage controlled amplifying circuit 2 of the multiplying circuit arrangement, the range of the operation region ARD is as small as about 50 mV from the center voltage of the control voltage V.sub.C. The problem is then presented that the gain G cannot be controlled to a predetermined value by keeping the control signal S.sub.C at a predetermined level. The prior art cannot therefore be applied to this kind of voltage controlled amplifier circuit 2.
FIG. 5 shows another proposal of a prior-art gain control amplifier in which a fixed gain differential amplifier 10A and a variable gain differential amplifier 20 are connected in cascade and the gain is controlled by varying the operation current of the second stage of the differential amplifier 20 by a control voltage E.sub.V.
Referring to FIG. 5, it will be seen that balance-type input terminals 1A and 2A supplied with, for example, a video signal are respectively connected to the bases of a pair of npn transistors 11 and 12 forming the differential amplifier 10A of the first stage. The emitters of the npn transistors 11A and 12 are respectively grounded via npn transistors 13 and 14 each serving as a constant current source, and a resistor 15 is connected between the emitters of the transistors 11A and 12. The collectors of the transistors 11A and 12 are connected through npn transistors 17, 18 connected in a diode fashion and a common resistor 16 to a terminal A to which a voltage Vcc is supplied.
The collectors of the transistors 11A and 12 forming the differential amplifier 10A are directly connected to the bases of a pair of npn transistors 21 and 22 forming the second stage of the differential amplifier 20. The voltage Vcc applied to the terminal A is supplied to the collectors of the transistors 21 and 22 through load resistors 23 and 24, respectively, while the emitters of the transistors 21 and 22 are grounded via a transistor 25 serving as a common constant current source. Similarly, the emitters of a pair of transistors 27 and 28 are grounded via a transistor 26 serving as a common constant current source, and a common constant voltage source 29 is connected to the bases of the transistors 27 and 28. The collectors of the transistors 27 and 28 are connected to the collectors of the transistors 21 and 22 to provide junctions B and C, respectively. Output terminals 3A and 4A are derived from the junctions B and C, respectively. The junction area of each of the transistors 25 and 26 is selected to be twice the junction area of each of the transistors 21, 22 and 27, 28.
The circuit in FIG. 5 also provides a reference constant current source 31 whose one end is grounded. The other end of the reference constant current source 31 is connected to a pnp transistor 32 connected in a diode fashion to the terminal A. The transistor 32 and a pnp transistor 33 connected to the former in a current mirror fashion and an npn transistor 34 connected in a diode fashion are serially connected between the terminal A and the ground. The transistor 34 is also connected to the transistors 13 and 14 forming the differential amplifier 10A in a current mirror fashion to form a constant current circuit.
In FIG. 5, reference numeral 40 designates a current control circuit. In the current control circuit 40, the emitters of a pair of pnp transistors 41 and 42 are connected to the terminal A through pnp transistors 43 and 44 each serving as a constant current source. A resistor 45 is connected between the emitters of the transistors 41 and 42. A variable control voltage source E.sub.V is connected through a control terminal 5A to the base of the transistor 41, whereas a constant voltage source 46 is connected to the base of the transistor 42. The collectors of the pnp transistors 41 and 42 are respectively grounded via npn transistors 47 and 48 connected in a diode fashion, and are further connected to the bases of the transistors 25 and 26 forming the next stage of the differential amplifier 20. The transistors 43 and 44 are connected to the diode-connected transistor 32 connected in a current mirror fashion.
With the above-mentioned circuit arrangement, the transistors 13 and 14 in the first differential amplifier 10A are connected to the transistor 32 through the transistors 34 and 33 in a double current mirror fashion, whereby a constant current equal to a reference current I.sub.0 of the constant current source 31 is flowed to the transistors 13 and 14.
When the control signal E.sub.V from the terminal 5A and a voltage E.sub.46 from the voltage source 46 are equal, the collector currents I.sub.41 and I.sub.42 of the transistors 41 and 42 are equal to the reference constant current of the constant current source 31. This gives I.sub.41 =I.sub.42 =I.sub.0. In that event, the transistors 26 and 25 in the second differential amplifier 20, which form a current mirror circuit with the transistors 47 and 48, produce collector currents, expressed as I.sub.26 =I.sub.25 =2I.sub.0.
The collector currents I.sub.41 and I.sub.42 of the transistors 41 and 42 in the current control circuit 40 are differentially changed in response to the change of the control voltage E.sub.V, whereby the collector currents I.sub.26 and I.sub.25 of the constant current source transistors 26 and 25 in the differential amplifier 20 are changed by the same ratios.
Assuming that resistance values of the load resistors 23 and 24 in the differential amplifier 20 are represented as R.sub.23 =R.sub.24 =R.sub.20 and that the resistance value of the resistor 15 in the first differential amplifier 10A is represented as R.sub.15, then the gain G from the input terminals lA, 2A to the output terminals 3A, 4A is expressed as given by the following equation (3) ##EQU3##
The fluctuation of direct current (DC) voltage components with the change of the operation current I.sub.25 of the transistor pair 21 and 22 is cancelled out by the fluctuation of DC voltage component with the reverse direction change of the operation current I.sub.26 of the other transistor pair 27 and 28. Thus, the levels of the DC voltage components appearing at the terminals 3A and 4A can be kept constant.
In the first differential amplifier 10A and the current control circuit 40, the resistors 15 and 45 are respectively connected between the emitters of the transistors 11A, 12 and 41, 42 so that linearity and dynamic range of the voltage controlled amplifier are improved as compared with the fundamental circuit arrangement in which the respective emitters of the transistors are directly connected.
In the prior-art gain controlled amplifier shown in FIG. 5, as described before, the transistors 13 and 14 in the first differential amplifier 10A constitute a double current mirror circuit together with the transistors 32 to 34, whereby a constant current equal to the reference current I.sub.0 of the constant current source 31 flows therethrough. The transistors 25 and 26 in the second differential amplifier 20 similarly forms the double current mirror circuit by interposing the transistors 43, 47 and 44, 48 between the transistors 25, 26 and the transistor 32.
Since the pnp transistors 41 and 42 are interposed in the middle stage of the double current mirror circuit, the characterstics such as h.sub.FE and the like of both the transistors 41 and 42 affect the operation currents I.sub.25 and I.sub.26 of the transistor pairs 21, 22 and 27, 28 of the differential amplifier 20, thus resulting in the gain G from the terminals 1A, 2A to the terminals 3A, 4A fluctuating.
If h.sub.FE of the transistors 41 and 42 fluctuates in a range of from, for example, the central value 60 to the minimal value 20, then the gain G fluctuates by, for example, about 0.4 dB. Thus, there is almost no way a tolerance of, for example, 0.5 dB can be obtained.